1. Field of the Invention
The invention relates to a method for manufacturing a package structure; more particularly, the invention relates to a method for manufacturing a chip package structure.
2. Description of Related Art
In recent years, with rapid progress of electronic technologies and advancement of high-tech electronic industry, human-oriented electronic products with superior performance have brought forth a new era and have been designed to cater to the trend of being light, thin, short, and small. Owing to said trend, circuit boards with fine pitch wires, compactness, and favorable performance have become one of the main media for holding a plurality of electronic devices (e.g., chips) and for electrically connecting the electronic devices to one another.
The flip-chip technology is a specific manner to package a chip over a circuit board. The circuit board has a plurality of pads thereon, and the circuit board can be electrically connected to the chip by means of a solder material on the pads through reflow. Recently, the number of signals transmitted among the electronic devices (e.g., chips) gradually increases, and therefore the number of pads required by the circuit board correspondingly increases. Due to the limited space in the circuit board, pitches among the pads are prone to become smaller and smaller.
A conventional chip package structure includes a chip, a substrate, a plurality of pads, a solder mask layer, and a plurality of solder bumps. The pads are located on a surface of a substrate. The solder mask layer covers the surface of the substrate and has a plurality of solder mask defined (SMD) openings respectively exposing the pads. The solder bumps respectively cover the pads and protrude from the openings. Through reflow, the substrate and the chip are electrically and structurally connected by means of the solder bumps located between the substrate and the chip.
To comply with the trend of fine pitch among the pads, the dimension of the openings of the solder mask layer is reduced, thus leading to an increase in the aspect ratio of the openings. This is detrimental to the printing or placement of large solder bumps; what is more, alignment between the solder bumps and the pads becomes more difficult. In addition, when the large solder bumps are placed on the pads and connected to the chip through reflow, the solder bumps subject to the heat generated through reflow are in a melted state. Since the pads are arranged on the surface of the substrate in a fine-pitch manner, bridge effects and short-circuit conditions may occur when the solder bumps are in the melted state during the reflow process; thereby, the requirement of fine-pitch cannot be satisfied.